In the last years, the memory market has been characterized by an increasing interest in high density devices and technology scaling has become more and more aggressive, both for memory core and circuitry, especially for the flash memory devices. While the technology is continuously improving to reduce the memory size, the scaling of standard NAND technologies has become more challenging due to parasitic effects which are relevant along with a more and more reduced cell pitch.
In a floating gate NAND flash memory, each cell transistor of the NAND flash memory comprises a floating gate which can selectively trap electrons for storing information. The floating gate is insulated from the well of the cell transistor by, e.g. oxide layer. To trap electrons into the floating gate, a programming operation is performed to a target cell. This programming operation may be performed, for example, by applying a high voltage to a gate terminal of the target cell and a ground voltage to a well or channel of the cell transistor. To remove or extract electrons being trapped in the floating gate, an erase operation is performed to the target cell. The erase operation may be performed, for example, by applying a high voltage to the well or channel of the cell transistor and a ground voltage to the gate terminal of the target cell. Usually, the erase operation is performed to a whole block of memory cells. Reading information stored in a target memory cell is performed by sensing current flowing through the target memory cell while applying an appropriate voltage to the gate terminal of the target cell.
One of those parasitic effects mentioned above, and the most critical in the recent years, is the floating gate coupling. Since floating gate distance is reduced with evolving technology, the interference due to the programming for neighboring cells becomes higher, thus causing error to the cell's reading or writing.
The parasitic phenomena and the higher and higher scaling capability has recently led to the development of new “charge trap” methods. In particular, according to a first kind of charge trap methods, a SONOS (semiconductor-oxide-nitride-oxide-semiconductor) or MONOS (metal-ONOS) structure is used for each memory cell. Moreover, according to a second type of charge trap methods, the memory array organization is the same as the previous method, in particular, the ones related to the floating gate flash memory. However, some differences exist due to new technology requirements and scaling.
In a conventional NAND memory array, a number of memory cells connected serially with one another form a group which is called a “string”. In other words, the drain of a memory cell or floating gate transistor of a string is coupled with the source of another memory cell or floating gate transistor of the same string. This connection is repeated to the other memory cells in the same manner. At each end of a string, a standard transistor is connected to the outmost floating gate transistor, i.e. memory cell, at both ends of the string and these two standard transistors are called drain selection transistor and source selection transistor, respectively. The string selection is performed by enabling or switching on the drain selection transistor and the source selection transistor. Usually, the selection transistors have positive threshold since they are standard transistors, and the selection transistors have reduced process variability.
In charge trap technology, the structure of the selection transistor is the same as that of the other memory cells including charge trap transistor, and this structure allows further array shrink by increasing its uniformity. However, this has a drawback in that the threshold of the selection transistors is affected by the same process dependency of the memory array transistors. Moreover, the threshold of the selection transistors is not a fixed positive value since charge trap transistor is used. The threshold of the selection transistors varies according to the amount of the electrons trapped in the respective gate terminal. Therefore, the threshold of the selection transistors should be properly controlled in this configuration.
To change the threshold voltage of a selection transistor into a different value, the selection transistor needs to be programmed or erased. It is required to program some target selection transistors among a group of selection transistors while preventing the other selection transistors to be influenced by the programming operation of the target selection transistors. Thus, “inhibit” should be considered when designing the method for programming the selection transistors. “Inhibit” means preventing programming operation from interfering with other cells which are not the target of the programming operation.
Conventional methods for programming or inhibiting should be thus enhanced in order to ensure a correct programming of the selection transistors and to avoid spurious programming on inhibited strings.
Therefore, the technical problem of the NAND flash programming methods according to prior art lies in that the threshold voltage of the selection transistors is not controlled precisely since no sophisticated programming operation for the selection transistors is available.